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SynaptiCAD appoints EuroEDA to distribute TimingDiagrammer, WaveFormer, Verilogger & TestBencher Pro tools in Europe

EuroEDA Limited, a value-added-reseller of design automation tools, today announced the addition of TimingDiagrammer, WaveFormer, Verilogger & TestBencher from SynaptiCAD Inc. to their portfolio of products.

EuroEDA markets & distributes a comprehensive range of EDA tools including schematic capture, circuit simulation, PCB layout, graphical entry and PLD/FPGA design, from their offices in Kettering, Northants. Founded by former Direct Insight Sales Director, Duncan Crowther, EuroEDA offers a range of highly complementary solutions that are sold through a combination of direct mail, telesales, internet marketing & field sales.

SynaptiCAD Inc. of Blacksburg, VA, was founded in 1993 and sells their range of timing diagram analysis and HDL test bench generation tools worldwide, both directly and through a network of international distributors. SynaptiCAD provides a complete range of products for high level design specification and verification for users of VHDL or Verilog based design methodologies.

TimingDiagrammer allows users to analyze designs in the early stages, before producing a schematic, and performs true full-range min/max timing analysis to eliminate timing violations and race conditions. TimingDiagrammer automatically calculates critical paths and adjusts for reconvergent fanout. A full range of documentation features and export formats are also supported.

WaveFormer combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a groundbreaking new EDA tool. WaveFormer allows users to automatically generate and simulate timing diagrams using common Boolean or registered logic equations, and can import or export waveforms to VHDL, Verilog, logic analyzers & pattern generators, SPICE, ABEL, and a variety of gate level simulators.

VeriLogger is a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with a powerful graphical test vector generator. Model testing is quickly accomplished and true bottom-up testing of every model in a design becomes a realistic proposition.

TestBencher generates reactive Verilog and VHDL test benches from language-independent timing diagrams drawn by the user. TestBencher users have direct access to the HDL code generation routines, and can add their own routines (or modify existing routines) to generate HDL code that meets their own unique test bench requirements. TestBencher contains all the features found in WaveFormer.

EuroEDA’s appointment coincides with the new version 6.0 of WaveFormer and TestBencher that offer significant new user-requested features, and performance enhancements over earlier versions. SynaptiCAD products are available now from EuroEDA Limited.

 

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