EuroEDA Limited, a value-added-reseller of low-cost design automation tools, today announced the addition of StateCAD & StateBench, from Visual Software Solutions to their portfolio of products.

EuroEDA markets & distributes a comprehensive range of EDA tools including schematic capture, circuit simulation, PCB layout, graphical entry, PLD/FPGA design & VHDL development from their offices in Kettering, Northants. Founded by former Direct Insight Sales Director, Duncan Crowther, EuroEDA offers a range of highly complementary solutions that are sold through a combination of direct mail, telesales, internet marketing & field sales.

Visual Software Solutions produce StateCAD, a well known PC based finite state machine (FSM) design tool that generates synthesizable HDL, and StateBench, an exciting new product that automatically creates HDL test benches from StateCAD state diagrams. Visual Software sells StateCAD & StateBench worldwide, both directly and through a network of international distributors.

StateCAD is the premier state diagram tool for Windows and includes many innovative features for developing and debugging graphical state machines. A series of Wizards guide the user through the various design stages, including initial state machine entry, FSM customization, creation of data flow structures, FSM optimization, HDL generation, debugging & documentation. Graphical state machine animation is provided for design observation, and new features such as automatic highlighting of state machine errors have been added to speed up the debugging process. StateCAD automatically checks for over 200 potential design problems including stuck-at states, conflicting conditions & output driver conflicts. All checks are performed before HDL generation, ensuring that bugs are eliminated early in the design process. StateCAD generates synthesizable HDL, including VHDL, Verilog, ABEL-HDL & Altera-HDL specifically optimized for the target synthesis tool to ensure optimal results. A C code output is also available. Enhanced documentation features have been included enabling the export of StateCAD designs to a variety of Windows documentation tools, including Microsoft Word.

StateBench is an exciting new tool that provides complete behavioral verification by creating VHDL or Verilog test benches from StateCAD state diagrams. StateBench automatically processes the entire design, assigning inputs, directing concurrent operation & checking outputs. Following test bench generation, StateBench validates timing parameters including input set-up times & output delays. Finally, StateBench facilitates complete design simulation through a combination of state diagram animation and a traditional waveform display. Design stimulation is uniquely accomplished through the state diagram with a series of simple mouse clicks. By clicking on various portions of the state diagram, the associated waveform output is displayed alongside the animated diagram, providing a visual and highly intuitive representation of the design’s behavior.