HDL Bencher begins by scanning a VHDL or Verilog design for entity declarations. The user selects the unit to be tested, and the timing parameters that must be met at synthesis. HDL Bencher responds automatically with a WaveTable template, which blends visual waveform information with table-based data entry seamlessly. The user then describes the stimulus and expected behavior using the mouse, a built-in pattern generator, and through the unique WaveTable spreadsheet interface.

Once the test patterns have been entered, HDL Bencher exports a simulation-ready test bench. The test bench includes all library declarations, stimulus & check statements, and error reporting routines needed to fully validate the design. No knowledge of HDL or scripting is needed to generate a test bench with HDL Bencher. HDL Bencher guarantees coherence between the test benches it generates and the design being tested. Whenever a change is made to the underlying HDL source, HDL Bencher automatically re-imports the design, updating the waveforms and test bench accordingly. Whenever signals are added, delete, renamed, or revised, HDL Bencher handles the updates automatically. HDL Bencher also allows the creation of dynamic test benches. Using a single waveform description, VHDL generics (and Verilog parameters) may be changed and HDL Bencher will automatically update the test bench.

HDL Bencher can be used to create waveform descriptions for architectural specification. Simply import the port definitions, draw the expected behavior and print out the waveforms. Later, as the the architectural body of a design is created, HDL Bencher will export the original waveforms as a behavioral test bench allowing the original  architectural specification to define the final test bench.