X-HDL is a powerful, "smart" bi-directional translation solution for VHDL and Verilog projects. X-HDL translates netlists, RTL code and many behavioural-level constructs with no requirement for special coding style or translation-control considerations. By performing "smart" translations without converting to an intermediate format, X-HDL retains all source code comments, retains logic structure and easily handles VHDL packages and multiple architectures per entity. Many language incompatibilities such as Verilog multiple assigned wires, Verilog blocking assignments, Verilog system functions, VHDL generates, VHDL user-defined types and VHDL records are all handled completely automatically.